The topography of a semiconductor structure is getting increasingly crucial in the manufacture of a multi-level integrated circuit device. The topography variation can result from different number of deposition layers in different regions of the semiconductor structure, in which an area with higher topography is more susceptible to the etching in a photolithographic process than a lower topography area.
Typically, a protection film is applied over the entire higher topographic area to prevent such area from damage of the etching. Nonetheless, the desired property of optical materials utilized, e.g., an anti-reflective coating to attenuate or absorb light reflected from the substrate surface into a subsequent photoresist, in the lithographic process is usually affected by the protection film.